静态数码管

一、整体框图本实验用到的是 六位八段数码管并且为了节省引脚用了74hc595芯片这样FPGA只需要用四个IO口就可以了。二、时序图设计首先是数码管显示程序的时序图让数码管每0.5s切换一个数显示。下面是74hc595模块以下是74hc595芯片的引脚介绍三、程序设计首先是seg_state模块的module seg_state(input wire clk ,input wire rst_n,output reg [5:0] sel, //位选output reg [7:0] seg //段选);parameter time_500ms 24_999_999 ; //0.5s//状态准备parameter SEG_0 8b1100_0000; //8hc0parameter SEG_1 8b1111_1001; //8hf9parameter SEG_2 8b1010_0100; //8ha4parameter SEG_3 8b1011_0000; //8hb0parameter SEG_4 8b1001_1001; //8h99parameter SEG_5 8b1001_0010; //8h92parameter SEG_6 8b1000_0010; //8h82parameter SEG_7 8b1111_1000; //8hf8parameter SEG_8 8b1000_0000; //8h80parameter SEG_9 8b1001_0000; //8h90parameter SEG_10 8b1000_1000; //8h88parameter SEG_11 8b1000_0011; //8h83parameter SEG_12 8b1100_0110; //8hc6parameter SEG_13 8b1010_0001; //8ha1parameter SEG_14 8b1000_0110; //8h86parameter SEG_15 8b1000_1110; //8h8ereg [24:0] cnt_500ms ;//reg cnt_flag ; //字符切换标志位reg [4:0] data ; //输出的0-F字符 num//parameteralways (posedge clk,negedge rst_n) //0.5s计数器beginif(~rst_n)cnt_500ms 25d0 ;else if( cnt_500ms time_500ms )cnt_500ms 25d0 ;elsecnt_500ms cnt_500ms 1b1 ;end//输出的0-F字符always (posedge clk,negedge rst_n)beginif(~rst_n)data 0 ;else if( data 5d15 cnt_500ms time_500ms )data 0 ;else if(cnt_500ms time_500ms )data data 1b1 ;elsedata data ;end//sel位选always (posedge clk ,negedge rst_n)beginif(~rst_n)sel 6b00_0000;elsesel 6b111_111;end//数码管显示 0-Falways (posedge clk ,negedge rst_n)beginif(~rst_n)seg 8d0 ;else case ( data )5d0 :seg SEG_0 ;5d1 :seg SEG_1 ;5d2 :seg SEG_2 ;5d3 :seg SEG_3 ;5d4 :seg SEG_4 ;5d5 :seg SEG_5 ;5d6 :seg SEG_6 ;5d7 :seg SEG_7 ;5d8 :seg SEG_8 ;5d9 :seg SEG_9 ;5d10:seg SEG_10 ;5d11:seg SEG_11 ;5d12:seg SEG_12 ;5d13:seg SEG_13 ;5d14:seg SEG_14 ;5d15:seg SEG_15 ;default: seg 4d0 ;endcaseendendmodule以下是hc595负责控制595模块把并行数据转成串行数据。module hc595(input wire clk ,input wire rst_n ,input wire [5:0] sel , //位选input wire [7:0] seg , //段选output reg ds , //串行数据output reg shcp , //移位寄存器时钟output reg stcp , //存储寄存器时钟output reg oe //输出使能低有效);reg [1:0] cnt ; //分频计数器reg [3:0] cnt_bit ; //传输位数计数器wire [13:0] data ; //数码管信号寄存//偶分频 cnt 50MHZ/412.5MHZalways (posedge clk ,negedge rst_n)beginif(~rst_n)cnt 0 ;else if( cnt 2d3 )cnt 0 ;elsecnt cnt 1b1;end//cnt_bit 传输位数计数器always (posedge clk ,negedge rst_n)beginif(~rst_n)cnt_bit 0;else if( cnt_bit 4d13 cnt 2d3)cnt_bit 0;else if ( cnt 2d3 )cnt_bit cnt_bit 1b1;elsecnt_bit cnt_bit ;end//seg dpseg[7]//将数码管信号寄存 位拼接assign data {seg[0],seg[1],seg[2],seg[3],seg[4],seg[5],seg[6],seg[7],sel};//shcp 移位寄存器时钟 12.5M的时钟always(posedge clk or negedge rst_n)beginif( ~rst_n )shcp 1b0;else if(cnt 2d2)shcp 1b1;elseshcp 1b0;end//stcp 存储寄存器时钟always(posedge clk ,negedge rst_n)beginif( ~rst_n )stcp 1b0;else if(cnt_bit 4d13 cnt3 )//高级计数器stcp 1b1;elsestcp 1b0;end//串行数据发送always (posedge clk , negedge rst_n)beginif(~rst_n)ds 1b0 ;else if( cnt 2d0 ) //保证数据每次都在cnt0的时候更新ds data [cnt_bit] ;end//oe输出使能低有效always (posedge clk, negedge rst_n)beginif(~rst_n)oe 1 ;elseoe 0 ; //一直有效endendmodule最后一个顶层module seg_595_state( ///顶层input wire clk ,input wire rst_n ,output wire stcp , //存储寄存器时钟output wire shcp , //移位寄存器时钟output wire ds , //串行数据output wire oe //输出使能低有效);wire [5:0] sel ; //位选信号wire [7:0] seg ; //段选信号hc595 hc595_inst (.clk (clk ),.rst_n (rst_n),.sel (sel ), //位选.seg (seg ), //段选.ds (ds ), //串行数据.shcp (shcp ), //移位寄存器时钟.stcp (stcp ), //存储寄存器时钟.oe (oe ) //输出使能低有效);seg_state seg_state_inst(. clk (clk ),. rst_n (rst_n ),. sel (sel ),. seg (seg ));endmodule